Nova Lake die shots show disaggregated design and TSMC N2P compute tiles

Die shots and video shared by Moore's Law Is Dead show the chip package design for Intel's upcoming Nova Lake lineup, which is expected in the first half of 2027. The architecture uses a disaggregated design with four tiles. The Nova Lake-HX configuration will feature 8P, 16E, and 4LPE cores, while the Nova Lake-H version will use 4P, 8E, and 4LPE cores. A high-end desktop Nova Lake-S chip could use 52 cores total, consisting of 16P, 32E, and 4LPE cores. Moore's Law Is Dead also notes a graphics tile configuration with 12 Xe-cores.

Manufacturing details indicate a split between vendors. Hub and peripheral controller tiles use Intel 18A-P, while smaller GPU tiles use Intel 3. Jaykihn reports that while Intel 18A-P was used to produce ES1 engineering samples between April and May 2026, the ES2 samples and future qualification samples will use TSMC's N2P process for the compute tiles.