YMTC plans mass production of 9,600 MT/s LPDDR5X memory

YMTC is preparing to begin mass production of LPDDR5X memory with speeds of 9,600 MT/s at its Fab 3 facility, according to Counterpoint Research. The company plans to use Vertical Channel Transistor (VCT) 4F² cell structure technology for these chips. Reports say the 4F² structure can reduce the physical footprint of a memory cell by about 33% compared to the industry-standard 6F² layout while using the same process node.

The company has already started low-scale manufacturing of DRAM. Counterpoint Research claims YMTC has been producing about 5,000 wafers per month of 16 Gb LPDDR5X-7500 at its Fab 2 plant since October 2025. To reach higher speeds, YMTC uses Xtacking 4.0 technology to fabricate memory cell wafers and peripheral logic circuits separately before combining them through hybrid bonding wafer-to-wafer stacking.

Micron says it will not bring 4F² DRAM to market and is instead focusing on the 6F² layout until 3D DRAM arrives. Micron President and Chief Technology and Products Officer Scott DeBoer says the advantages of 4F² are "a bit of a myth" because capacitor pitch defines the DRAM.