Intel and AMD publish ACE v2 and AVX10.3 specs with GCC patches

Intel and AMD have published the ACE v2 and AVX10.3 specifications through the x86 Ecosystem Advisory Group. The combined document adds 4-bit data types alongside FP16, FP32, and FP64 modes to the ACE matrix engine. It also advances general-purpose vector code with AVX10.3, which splits into four instruction groups.

Image: Phoronix

Enabling AVX10.3 in the compiler automatically implies AVX10.2 and AVX10V2AUX support. The FP64 variant requires a register pair starting on an even-numbered zmm register, mirroring requirements from older Xeon Phi instructions. Intel engineer Haochen Jiang posted matching GCC compiler patches on the mailing list alongside the spec release.

AVX10.2 and the first version of ACE do not have support from any shipping processors yet. The 2028 to 2029 window marks when the first CPUs with ACE v2 and AVX10.3 are expected, according to reports.