TSMC A14 node expects 19% SRAM density improvement

TSMC says its A14 NanoFlex Pro platform will feature an SRAM 6T bitcell smaller than 0.017 µm². This represents a 19% density increase compared to the 0.021 µm² cells used since the N5 node arrived in 2020. The company is scheduled to present these details at the IEDM conference in San Francisco this December.

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Compared to the N2 node, TSMC claims the A14 node offers up to 15% higher speeds at the same power level or up to 30% power reduction at the same frequency. TSMC also expects a 20% increase in logic density. The node will include through-silicon vias, high-performance MiM capacitors, and a redistribution layer that supports a 4.5 µm SoIC bond pitch.

TSMC is currently running pilot production to allow customers to evaluate designs. If pilot production proceeds without major issues, risk production is set for 2027 and high-volume manufacturing is planned for 2028 in Taiwan. TSMC says the production schedule may accelerate by a few months if no significant challenges arise next year. The first A14 version will use conventional front-side power delivery, while a Super Power Rail backside variant is planned to follow about a year later.

Reports say the reported bitcell size is a test-structure number rather than a final product spec. High-current cells used for L1 and L2 caches are typically larger than these high-density cells.